bit per component と bit per pixel との関係はこれ

RGBとYCC444は bit per component of Y * 3 = bit per pixel。
YCC422は1pixel毎のCbCrになるので、bit per component of Y * 2 = bit per pixel。
YCC420は1line毎にCbCrを切り替え、1pixel毎のCbもしくはCrなので、bit per component of Y * 1.5 = bit per pixel。

参照:
http://www.eizo.co.jp/products/tech/files/2010/WP10-009.pdf
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Basic of GTC(Global Time Code) in DP

- GTC reference clock period is 1ns.
- GTC reference clock is adjustable.
- FIRST_COMMAND_EDGE is AUX first rising edge after sync commmand.

- In case of that DPTX is master.
-- DPRX record GTC accumulator at the arrival of FIRST_COMMAND_EDGE for the write transaction.
-- DPRX record GTC accumulator at the time it has finished receiving the 32-bit TX GTC value(GTC_Reception).
-- DPTX record GTC accumulator at the arrival of FIRST_COMMAND_EDGE for the reply transaction(RX_GTC_FREQ_LOCK_DONE).

- In case of that DPRX is master.
-- DPTX record GTC accumulator at the arrival of FIRST_COMMAND_EDGE for the reply transaction.
-- DPTX record GTC accumulator at the time it has finished receiving the 32-bit RX GTC value(GTC_Reception).
-- DPRX record GTC accumulator at the arrival of FIRST_COMMAND_EDGE for the write transaction(TX_GTC_FREQ_LOCK_DONE).
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cec arbitration

When message is layered until start ~ bit4, initiator is changed to follower.
After that, follower wait for Signal Free Time.

Frame period is defined on 3/5/7 data bit periods.
It is defined as "Signal Free Time" in hdmi spec.
Unit time is 2.4 ms.
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There are two kinds of target massage for specific device or broadcast in cec

In that case, of destination address are 0~14, the target is specific device. In that case, of destination address are 15, target is multiple, that is broadcast. Broadcast transfer is initiated to multiple device and only ignored device response back. Another word, it is not possible to identify ignored device.
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cec frame format

The details of each block of the frame are given in the subsequent sections.

1.Start
2.Header Block
3.Opcode Block
4.Operand Blocks

The data kind of Operand Blocks is defined on Parameters:[...] of Table X Message Descriptions.
The data byte of Operand Blocks is defined on Length of Table X Operand Descriptions.
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DP have Native AUX and I2C over AUX transaction

Request command is below.

1. command[3:0]
[3] I2C over AUX:0, Native AUX:1
[2] I2C over AUX:Middle-of-Transaction bit, Native AUX:NA
[1] I2C over AUX:Write_Status_Update_Request enable bit, Native AUX:NA
[0] Write:0, Read:1
2. address
3. length byte
4. N data byte (when write)

Reply command status have three kind, ack, nack and deffer.

Slave address for I2C over AUX is specified in standard.
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Note DP Control Symbols


K-code Single-stream Multi-stream
K28.0 0x1C SR(Scrambler Reset) GP1 index 2
K28.1 0x3C CP(Content Protection) GP2 rsvd
K28.2 0x5C SS(SDP Start) GP1 index 3
K28.3 0x7C BF GP1 index 4
K28.4 0x9C rsvd GP2 rsvd
K28.5 0xBC BS(Blanking Start) GP2 SR
K28.6 0xDC rsvd GP1 index 5
K28.7 0xFC rsvd GP2 rsvd
K23.7 0xF7 FE(Fill End) GP1 index 0
K27.7 0xFB BE(Blanking End) GP1 index 1
K29.7 0xFD SE(SDP End) GP1 index 6
K30.7 0xFE FS(Fill Start) GP1 index 7

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DP Link Training is defined in standard 3.5.1.2

Link training between DisplayPort source and sink devices consists of two distinct tasks.
These tasks are clock recovery and channel equalization/symbol-lock/inter-lane alignment.

- Clock recovery phase
Clock recovery is the operation of recovering the link clock from the link data stream being sent by the source. This circumvents the need of any external clock for the sink to recover the data being sent bysSource.
In this stage, the sink receiver locks the clock recovery PLL to the repetition of D10.2 data symbols which are sent by the source.
The repetition of D10.2 symbols is called TPS1 pattern. D10.2 symbols carry the bit transitions (from 0 to 1, and vice-versa) every bit interval, which make them most suitable for clock recovery at the receiver end.

- Channel equalization/symbol-lock/inter-lane alignment phase
Equalization is needed to recover the symbols sent by the source.
Symbol-lock and inter-lane alignment must be achieved by the end of this phase.
Source sends series of data and control symbols to the sink, for the sink to lock to the symbols and do inter-lane alignment. These series are either TPS2 (comprised of K28.5, D11.6 and D10.2) or TPS3 (comprised of K28.5, D10.2 and D30.3) pattern.

- TPS1
D10.2 -> 0x4A
without scrambling

- TPS2
K28.5 -> 0xBC
D11.6 -> 0xCB
K28.5 -> 0xBC
D11.6 -> 0xCB
D10.2 -> 0x4A
without scrambling

- TPS3
K28.5 -> 0xBC
D10.2 -> 0x4A
K28.5 -> 0xBC
D30.3 -> 0x7E
without scrambling

- TPS4
K28.0 -> 0x1C
K28.5 -> 0xBC
K28.0 -> 0x1C
248 00hs

reference:
http://community.cadence.com/cadence_blogs_8/b/ip/archive/2015/03/23/link-training-_2d00_-establishing-communication-between-displayport-source-and-sink-devices
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Grasp 8B/10B Code

The 8B/10B data and control codes are referred to as Dx.y and Kx.y, respectively. The 8-bit byte – H G F E D C B A, where H is the most significant bit (MSB) and A is the significant bit (LSB) – is broken up into two groups, x and y, where x is the five lower bits (E D C B A) and y is the three upper bits (H G F).

reference:
https://www.altera.com/en_US/pdfs/literature/hb/agx/agx_52004.pdf
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