Note DP Control Symbols


K-code Single-stream Multi-stream
K28.0 0x1C SR(Scrambler Reset) GP1 index 2
K28.1 0x3C CP(Content Protection) GP2 rsvd
K28.2 0x5C SS(SDP Start) GP1 index 3
K28.3 0x7C BF GP1 index 4
K28.4 0x9C rsvd GP2 rsvd
K28.5 0xBC BS(Blanking Start) GP2 SR
K28.6 0xDC rsvd GP1 index 5
K28.7 0xFC rsvd GP2 rsvd
K23.7 0xF7 FE(Fill End) GP1 index 0
K27.7 0xFB BE(Blanking End) GP1 index 1
K29.7 0xFD SE(SDP End) GP1 index 6
K30.7 0xFE FS(Fill Start) GP1 index 7

2017-09-22 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop

DP Link Training is defined in standard 3.5.1.2

Link training between DisplayPort source and sink devices consists of two distinct tasks.
These tasks are clock recovery and channel equalization/symbol-lock/inter-lane alignment.

- Clock recovery phase
Clock recovery is the operation of recovering the link clock from the link data stream being sent by the source. This circumvents the need of any external clock for the sink to recover the data being sent bysSource.
In this stage, the sink receiver locks the clock recovery PLL to the repetition of D10.2 data symbols which are sent by the source.
The repetition of D10.2 symbols is called TPS1 pattern. D10.2 symbols carry the bit transitions (from 0 to 1, and vice-versa) every bit interval, which make them most suitable for clock recovery at the receiver end.

- Channel equalization/symbol-lock/inter-lane alignment phase
Equalization is needed to recover the symbols sent by the source.
Symbol-lock and inter-lane alignment must be achieved by the end of this phase.
Source sends series of data and control symbols to the sink, for the sink to lock to the symbols and do inter-lane alignment. These series are either TPS2 (comprised of K28.5, D11.6 and D10.2) or TPS3 (comprised of K28.5, D10.2 and D30.3) pattern.

- TPS1
D10.2 -> 0x4A
without scrambling

- TPS2
K28.5 -> 0xBC
D11.6 -> 0xCB
K28.5 -> 0xBC
D11.6 -> 0xCB
D10.2 -> 0x4A
without scrambling

- TPS3
K28.5 -> 0xBC
D10.2 -> 0x4A
K28.5 -> 0xBC
D30.3 -> 0x7E
without scrambling

- TPS4
K28.0 -> 0x1C
K28.5 -> 0xBC
K28.0 -> 0x1C
248 00hs

reference:
http://community.cadence.com/cadence_blogs_8/b/ip/archive/2015/03/23/link-training-_2d00_-establishing-communication-between-displayport-source-and-sink-devices
2017-09-22 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop

Grasp 8B/10B Code

The 8B/10B data and control codes are referred to as Dx.y and Kx.y, respectively. The 8-bit byte – H G F E D C B A, where H is the most significant bit (MSB) and A is the significant bit (LSB) – is broken up into two groups, x and y, where x is the five lower bits (E D C B A) and y is the three upper bits (H G F).

reference:
https://www.altera.com/en_US/pdfs/literature/hb/agx/agx_52004.pdf
2017-09-22 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop

HDMI pixel packing phase informatin is sent by GCP

About HDMI deep color pixel packing, packing phase information of last pixel is sent from source, sink must adjust start phase to un-packing.

Default_Phase is 1, phase always starts from zero.
2017-09-15 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop

Understanding TMDS Clock Frequency and TMDS Character Rate

"TMDS Character Rate" represents the transmission amount of "TMDS Character" per second in each TMDS data channel and is expressed in units called "Mega-characters per second, per channel (Mcsc)".
In HDMI version 2.0 or later, it was decided that TMDS Clock Frequency = TMDS Character Rate / 4 only when "TMDS Character Rate" exceeds 340 Mcsc.

ref:
http://www.hdmi-navi.com/tmds/
2017-07-27 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop

Digital Audio Fromat is basicaly defined as IEC 60958

Consist of 192 frames, 2 sub frames in a frame.
Sub frame have 4 bit preamble, 24 bit payload, 4 bit additional flag.

ref:
http://probe.hamazo.tv/e1746986.html
http://www.tritech.tv/column/aesebu.html
2017-06-06 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop

Bounce is almost same meaning with chattering

Mechanical switches do not make or break a connection cleanly due to microscopic conditions on the contact surface.
This is referred to as "Switch Bounce" and can cause problems in digital circuits.

ref:
https://protostack.com.au/2010/03/debouncing-a-switch/
2017-05-17 : Work-Product-Spec : コメント : 0 : トラックバック : 0
Pagetop
ホーム  次のページ »

プロフィール

zive

Author:zive
大阪在住、男

ブログ検索

月別アーカイブ

FC2カウンター