Use tran/tranif0/tranif1 to select connection

tran is only connect.
tranif0/tranif1 are connected when control signal asserted.

ref:
http://rilo.moo.jp/vlog/verilog02_6.html
2017-05-10 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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Grasp uvm extend chain

Parameter is usable.
base_test can be changed to user test class.


class UvmVSeq #(type org_seq = uvm_sequence) extends org_seq;
class UvmVSeqr #(type org_seqr = uvm_sequencer) extends org_seqr;
class UvmTest #(type org_test = uvm_test) extends org_test;


To restrict access to class, use "local" to variable, use "virtual" to task and function.
2017-04-27 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

ISP is In-System Programming

It is a technique where a programmable device is programmed after the device is placed in a circuit board.

ref:
https://www.eetools.com/downloads/understanding-in-system-programming.pdf
2017-03-13 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Incisive of Cadence simulator is changed to Xcelium

Command line change as irun -> xrun.
Last version of Incisive is 15.2.
Xcelium have two kind of licenses as Multi core and Single core.
2017-03-06 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Use $nc_force for vhdl code on incisive

Normal force command can not be used.

Each bits have to be write "'0/1'".

For cross module signal referencing, use $nc_mirror.

ref:
http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals/cdn_ncmirror_donation.pdf
2017-01-10 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

The class parameter of Env and VSqr and VSeq have to be same

Because, Vsqr and Vseq have reference pointer of Env.
If each parameter are not same, compile error occurs.
2016-11-25 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop
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