Simple verilog simulation template

To reproduce any issue.


reg test_reset;
reg test_clk;
reg [1:0] test_data;

initial begin
test_reset = 0;
test_clk = 0;
test_data[0] = 0;

repeat (10) @(posedge test_clk) test_reset = 1;
repeat (10) @(posedge test_clk) test_data[0] = 1;
end

always begin
#10ns;
test_clk <= ~test_clk;
end

always @(posedge test_clk or negedge test_reset) begin
if (~test_reset) test_data[1] <= 0;
else test_data[1] <= data[0];
end

2017-10-13 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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Basically ARM is little endian

So, when cleaning x included 32 bit data, following code can be used.


uint8_t bdata[4];
uint32_t *wdata;
wdata = (uint32_t *)bdata;
*wdata = (uint32_t *)(addr);
return bdata[align]; // little endian

2017-09-26 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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Simple clock recovery implementation by system verilog


bit recovered_clock = 0;
initial begin : recclk
int unsigned div = 10;
bit reverse = 0;
int avarage = 10;

bit simtime_update = 0;
int unsigned simtime[2];
int unsigned simtime_diff;
int unsigned simtime_div_half = 0;
int unsigned simtime_div_half_queue[$];
int cycle;
bit error = 0;

forever begin
cycle = 0;
if (simtime_div_half != 0) begin
fork begin
while (cycle < div) begin
recovered_clock = ~reverse;
#(simtime_div_half);
recovered_clock = reverse;
if (cycle != (div-1)) #(simtime_div_half);
cycle++;
end
end join_none
end
@(posedge refclk);
disable fork;
if (cycle != div) error = 1;
else error = 0;
simtime[simtime_update] = $time;
if (simtime_update) begin
simtime_diff = (simtime[1] - simtime[0]);
simtime[0] = simtime[1];
simtime_div_half = simtime_diff / (div*2);
for (int i = 0; i < simtime_div_half_queue.size(); i++) begin
simtime_div_half = simtime_div_half + simtime_div_half_queue[i];
end
simtime_div_half = simtime_div_half / (simtime_div_half_queue.size() + 1);
simtime_div_half_queue.push_back(simtime_div_half);
if ((avarage - 1) < simtime_div_half_queue.size()) simtime_div_half_queue.pop_front();
end
simtime_update = 1;
end
end

2017-07-06 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Edge ditect for combination logic on verification

It would be pickup-ed delta edge by using posedge.
So, add another condition as follows.


@(posedge signal && signal !== 1'bx or negedge signal && signal !== 1'bx)

2017-06-08 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Use tran/tranif0/tranif1 to select connection

tran is only connect.
tranif0/tranif1 are connected when control signal asserted.

ref:
http://rilo.moo.jp/vlog/verilog02_6.html
2017-05-10 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Grasp uvm extend chain

Parameter is usable.
base_test can be changed to user test class.


class UvmVSeq #(type org_seq = uvm_sequence) extends org_seq;
class UvmVSeqr #(type org_seqr = uvm_sequencer) extends org_seqr;
class UvmTest #(type org_test = uvm_test) extends org_test;


To restrict access to class, use "local" to variable, use "virtual" to task and function.
2017-04-27 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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