Incisive/VCSでシミュレーターライセンス待ちオプションはこれ

Incisive:-licqueue
VCS:+vcs+lic+wait

VIPはまた別です。
Cadenceは環境変数"CADENCE_VIP_LIC_Q_TIMEOUT"で制御します。

Incisiveに関して、ライセンス待ち状態になると、最初に参照したライセンスサーバーでしか待たず、他のライセンスサーバーが空いてもそこにあるライセンスを確認しません。それを回避するためには別の環境変数が必要です。

参照:
https://github.com/cjdrake/AES/blob/master/Makefile
http://haell.com/~wyrm/works/academia/CSUS/cpe142/project_phase_3/vcs-h
https://github.com/wataruya/jenkins_vm/blob/master/RUNME.csh
2017-12-04 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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imc のコマンドラインオプションを把握しておこう

これくらい覚えておけばいいでしょう。


-batch run in non-gui mod
-gui run in gui mode
-init <file> run tcl commands in the given file at startup
-load <run> load given run at the start
-load_refinement <ref> load ref run at the start

2017-11-09 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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VCS Fine-Grained Parallelism option is added

Add "-fgp" option to use FGP.
Compile partitioning is divided by APP about DUT limited.
Additional license is necessary.
2017-11-01 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Cadence Jules is integrated solution for power estimation

Necessary input are below.

- rtl or layout net list
- liberty
- stimulus

Relation is easy with Voltus for IR drop sign off.
Replacing library cell is possible. However, the good point to use RTL become none.
Redundant power can be reported.
2017-10-26 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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The order of clock and data in Zero-Cycle may be changed by passing through module port

To avoid this behavior, delta delay insertion is necessary after non-blocking re-timing.
2017-10-18 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Simple verilog simulation template

To reproduce any issue.


reg test_reset;
reg test_clk;
reg [1:0] test_data;

initial begin
test_reset = 0;
test_clk = 0;
test_data[0] = 0;

repeat (10) @(posedge test_clk) test_reset = 1;
repeat (10) @(posedge test_clk) test_data[0] = 1;
end

always begin
#10ns;
test_clk <= ~test_clk;
end

always @(posedge test_clk or negedge test_reset) begin
if (~test_reset) test_data[1] <= 0;
else test_data[1] <= data[0];
end

2017-10-13 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

Basically ARM is little endian

So, when cleaning x included 32 bit data, following code can be used.


uint8_t bdata[4];
uint32_t *wdata;
wdata = (uint32_t *)bdata;
*wdata = (uint32_t *)(addr);
return bdata[align]; // little endian

2017-09-26 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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Simple clock recovery implementation by system verilog


bit recovered_clock = 0;
initial begin : recclk
int unsigned div = 10;
bit reverse = 0;
int avarage = 10;

bit simtime_update = 0;
int unsigned simtime[2];
int unsigned simtime_diff;
int unsigned simtime_div_half = 0;
int unsigned simtime_div_half_queue[$];
int cycle;
bit error = 0;

forever begin
cycle = 0;
if (simtime_div_half != 0) begin
fork begin
while (cycle < div) begin
recovered_clock = ~reverse;
#(simtime_div_half);
recovered_clock = reverse;
if (cycle != (div-1)) #(simtime_div_half);
cycle++;
end
end join_none
end
@(posedge refclk);
disable fork;
if (cycle != div) error = 1;
else error = 0;
simtime[simtime_update] = $time;
if (simtime_update) begin
simtime_diff = (simtime[1] - simtime[0]);
simtime[0] = simtime[1];
simtime_div_half = simtime_diff / (div*2);
for (int i = 0; i < simtime_div_half_queue.size(); i++) begin
simtime_div_half = simtime_div_half + simtime_div_half_queue[i];
end
simtime_div_half = simtime_div_half / (simtime_div_half_queue.size() + 1);
simtime_div_half_queue.push_back(simtime_div_half);
if ((avarage - 1) < simtime_div_half_queue.size()) simtime_div_half_queue.pop_front();
end
simtime_update = 1;
end
end

2017-07-06 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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