DP Link Training is defined in standard 3.5.1.2

Link training between DisplayPort source and sink devices consists of two distinct tasks.
These tasks are clock recovery and channel equalization/symbol-lock/inter-lane alignment.

- Clock recovery phase
Clock recovery is the operation of recovering the link clock from the link data stream being sent by the source. This circumvents the need of any external clock for the sink to recover the data being sent bysSource.
In this stage, the sink receiver locks the clock recovery PLL to the repetition of D10.2 data symbols which are sent by the source.
The repetition of D10.2 symbols is called TPS1 pattern. D10.2 symbols carry the bit transitions (from 0 to 1, and vice-versa) every bit interval, which make them most suitable for clock recovery at the receiver end.

- Channel equalization/symbol-lock/inter-lane alignment phase
Equalization is needed to recover the symbols sent by the source.
Symbol-lock and inter-lane alignment must be achieved by the end of this phase.
Source sends series of data and control symbols to the sink, for the sink to lock to the symbols and do inter-lane alignment. These series are either TPS2 (comprised of K28.5, D11.6 and D10.2) or TPS3 (comprised of K28.5, D10.2 and D30.3) pattern.

referece:
http://community.cadence.com/cadence_blogs_8/b/ip/archive/2015/03/23/link-training-_2d00_-establishing-communication-between-displayport-source-and-sink-devices
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