Simple clock recovery implementation by system verilog


bit recovered_clock = 0;
initial begin : recclk
int unsigned div = 10;
bit reverse = 0;
int avarage = 10;

bit simtime_update = 0;
int unsigned simtime[2];
int unsigned simtime_diff;
int unsigned simtime_div_half = 0;
int unsigned simtime_div_half_queue[$];
int cycle;
bit error = 0;

forever begin
cycle = 0;
if (simtime_div_half != 0) begin
fork begin
while (cycle < div) begin
recovered_clock = ~reverse;
#(simtime_div_half);
recovered_clock = reverse;
if (cycle != (div-1)) #(simtime_div_half);
cycle++;
end
end join_none
end
@(posedge refclk);
disable fork;
if (cycle != div) error = 1;
else error = 0;
simtime[simtime_update] = $time;
if (simtime_update) begin
simtime_diff = (simtime[1] - simtime[0]);
simtime[0] = simtime[1];
simtime_div_half = simtime_diff / (div*2);
for (int i = 0; i < simtime_div_half_queue.size(); i++) begin
simtime_div_half = simtime_div_half + simtime_div_half_queue[i];
end
simtime_div_half = simtime_div_half / (simtime_div_half_queue.size() + 1);
simtime_div_half_queue.push_back(simtime_div_half);
if ((avarage - 1) < simtime_div_half_queue.size()) simtime_div_half_queue.pop_front();
end
simtime_update = 1;
end
end

2017-07-06 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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zive

Author:zive
大阪在住、男

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