Edge ditect for combination logic on verification

It would be pickup-ed delta edge by using posedge.
So, add another condition as follows.


@(posedge signal && signal !== 1'bx or negedge signal && signal !== 1'bx)

2017-06-08 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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Use tran/tranif0/tranif1 to select connection

tran is only connect.
tranif0/tranif1 are connected when control signal asserted.

ref:
http://rilo.moo.jp/vlog/verilog02_6.html
2017-05-10 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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Grasp uvm extend chain

Parameter is usable.
base_test can be changed to user test class.


class UvmVSeq #(type org_seq = uvm_sequence) extends org_seq;
class UvmVSeqr #(type org_seqr = uvm_sequencer) extends org_seqr;
class UvmTest #(type org_test = uvm_test) extends org_test;


To restrict access to class, use "local" to variable, use "virtual" to task and function.
2017-04-27 : Work-Product-Verification : コメント : 0 : トラックバック : 0
Pagetop

ISP is In-System Programming

It is a technique where a programmable device is programmed after the device is placed in a circuit board.

ref:
https://www.eetools.com/downloads/understanding-in-system-programming.pdf
2017-03-13 : Work-Product-Verification : コメント : 0 : トラックバック : 0
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